This Invention relates to scalable processing networks, in particular but not restricted to processing networks employing concurrent microprocessor technology used in the communications industry.
A common type of processor function is to locate in a memory store all occurrences of a desired value, and then to determine the sum of all occurrences. Typically this is achieved through a series of synchronous matching actions wherein each memory store location is searched and matched in turn. However, this implementation is wasteful of time and processor cycles.
In a case where a processor has an associated local memory store, for example the multiprocessor implementation of Single Instruction Multiple Data (SIMD) processors which is the subject of the applicant's European Patent published as EP 0983556, the search and summation function as described in the above paragraph may be carried out through a type of inter-processor communication known as ‘alternation’.
Efficient inter-processor communications in SIMD data parallel processors is paramount to performance. Algorithms that require efficient inter-processor communications are the so-called, binary ‘divide-and-conquer’ algorithms, whereby the multitude of processors in a data parallel architecture are sub-divided into even/odd subsets in an efficient manner, enable the efficient processing of large amounts of data.